In the context of hardware and software systems, formal verification is the act of proving the correctness of algorithm designs using formal methods of mathematics. Formal verification has become a well-established practice in parts of the hardware design industry due to the ability of formal verification methods to deal with the increasing complexity of hardware systems, such as multi-core architectures. As a result of the subtle interactions between architectural components, it is difficult to exercise a realistic set of possibilities by simulation, which is the process often used to test a system design. Simulation, or model checking, explores a model of the hardware system being tested and determines whether the model meets a given specification. Simulation methods may be efficient at exposing bugs, but are based on incomplete methods which cannot achieve full evaluation of all operand combinations over all states. As a main alternative to simulation, formal verification proves the system design functions correctly on all possible inputs and closes the state space coverage gap encountered when using simulation.